Dr Yun Wang

The mixed caesium and formamidinium lead triiodide perovskite system (Cs1−xFAxPbI3) in the form of quantum dots (QDs) offers a pathway towards stable perovskite-based photovoltaics and optoelectronics. However, it remains challenging to synthesize such multinary QDs with desirable properties for high-performance QD solar cells (QDSCs). Here we report an effective oleic acid (OA) ligand-assisted cation-exchange strategy that allows controllable synthesis of Cs1−xFAxPbI3 QDs across the whole composition range (x = 0–1), which is inaccessible in large-grain polycrystalline thin films. In an OA-rich environment, the cross-exchange of cations is facilitated, enabling rapid formation of Cs1−xFAxPbI3 QDs with reduced defect density. The hero Cs0.5FA0.5PbI3 QDSC achieves a certified record power conversion efficiency (PCE) of 16.6% with negligible hysteresis. We further demonstrate that the QD devices exhibit substantially enhanced photostability compared with their thin-film counterparts because of suppressed phase segregation, and they retain 94% of the original PCE under continuous 1-sun illumination for 600 h.

This paper investigates how the thermal diffusion of boron in silicon is influenced by a high energy fluorine implant with a dose in the range 5x10(14)-2.3x10(15) cm(-2). Secondary Ion Mass Spectroscopy (SIMS) profiles of boron marker layers are presented for different fluorine doses and compared with fluorine profiles to establish the conditions under which thermal boron diffusion is suppressed. The (SIMS) profiles show significantly reduced boron thermal diffusion above a critical F+ dose of 0.9-1.4x10(15) cm(-2). Fitting of the measured boron profiles gives suppressions of the boron thermal diffusion coefficient by factors of 1.9 and 3.7 for F+ implantation doses of 1.4x10(15) and 2.3x10(15) cm(-2), respectively. The suppression of boron thermal diffusion above the critical fluorine dose correlates with the appearance of a shallow fluorine peak on the (SIMS) profile in the vicinity of the boron marker layer. This shallow fluorine peak is present in samples with and without boron marker layers, and hence it is not due to a chemical interaction between the boron and the fluorine. Analysis of the (SIMS) profiles and cross-section Transmission Electron Microscope micrographs suggests that it is due to the trapping of fluorine at vacancy-fluorine clusters, and that the suppression of the boron thermal diffusion is due to the effect of the clusters in suppressing the interstitial concentration in the vicinity of the boron profile

This paper studies how boron transient enhanced diffusion (TED) and boron thermal diffusion in Si1-xGex are influenced by a high-energy fluorine implant at a dose in the range 5 x 10(14) cm(-2) to 1 x 10(16) cm(-2). Secondary ion mass spectroscopy (SIMS) profiles of boron marker layers are presented for different fluorine doses and compared with fluorine SIMS profiles and transmission electron microscopy (TEM) micrographs to establish the conditions under which boron diffusion is suppressed. The SIMS profiles show that boron thermal diffusion is reduced above a critical F+ dose of 7-9 x 10(14) cm(-2), whereas boron TED is suppressed at all doses. Fitting of the measured boron profiles gives suppressions of boron TED diffusion coefficients by factors of 6.8, 10.6, and 12.9 and of boron thermal diffusion coefficient by factors of 1.9, 2.5, and 3.5 for F+ implantation doses of 9 x 10(14), 1.4 x 10(15), and 2.3 x 10(15) cm(-2) respectively. The reduction of boron thermal diffusion above the critical fluorine dose correlates with the appearance of a shallow fluorine peak on the SIMS profile in the vicinity of the boron marker layer, which is attributed to vacancy-fluorine clusters. This reduction of boron thermal diffusion is explained by the effect of the clusters in suppressing the interstitial concentration in the Si1-xGex layer. The suppression of boron TED correlates with a deep fluorine peak around the range of the fluorine implant and TEM micrographs show that this peak is due to a band of dislocation loops. This suppression of boron TED is explained by the retention of interstitials in the dislocation, loops, which suppresses their backflow to the surface. The fluorine SIMS profiles show that the fluorine concentration in the Si1-xGex layer increases with increasing germanium concentration and that the fluorine concentration in the Si1-xGex layer after anneal is much higher than after implant. This indicates that fluorine is transported into the Si1-xGex layer from the adjacent silicon, and is explained by the lower formation energy for vacancies in Ge than in Si. This accumulation of fluorine in the Si1-xGex layer during anneal is advantageous for devices like SiGe heterojunction bipolar transistors, where the boron must be kept within the Si1-xGex layer.

We present raised source/drain MOSFET devices with channel lengths down to 50 nm. The raised source/drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre-epitaxy process that eliminates the need for a pre-epitaxy bake in hydrogen has been developed. In this study, we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper, we show how short channel performance can be retrieved by adding raised source/drain structures, and how increasing the thickness of these structures improves these parameters further.

This paper studies how boron transient enhanced diffusion (TED) and boron thermal diffusion in Si1-xGex are influenced by a high-energy fluorine implant at a dose in the range 5 x 1014 cm-2 to 1 x 1016 cm-2. Secondary ion mass spectroscopy (SIMS) profiles of boron marker layers are presented for different fluorine doses and compared with fluorine SIMS profiles and transmission electron microscopy (TEM) micrographs to establish the conditions under which boron diffusion is suppressed. The SIMS profiles show that boron thermal diffusion is reduced above a critical F+ dose of 7 - 9 x 1014 cm-2, whereas boron TED is suppressed at all doses. Fitting of the measured boron profiles gives suppressions of boron TED diffusion coefficients by factors of 6.8, 10.6, and 12.9 and of boron thermal diffusion coefficient by factors of 1.9, 2.5, and 3.5 for F+ implantation doses of 9 x 1014, 1.4 x 1015, and 2.3 x 1015 cm-2 respectively. The reduction of boron thermal diffusion above the critical fluorine dose correlates with the appearance of a shallow fluorine peak on the SIMS profile in the vicinity of the boron marker layer, which is attributed to vacancy-fluorine clusters. This reduction of boron thermal diffusion is explained by the effect of the clusters in suppressing the interstitial concentration in the Si/sub 1-x/Ge/sub x/ layer. The suppression of boron TED correlates with a deep fluorine peak around the range of the fluorine implant and TEM micrographs show that this peak is due to a band of dislocation loops. This suppression of boron TED is explained by the retention of interstitials in the dislocation loops, which suppresses their backflow to the surface. The fluorine SIMS profiles show that the fluorine concentration in the Si1-xGex layer increases with increasing germanium concentration and that the fluorine concentration in the Si1-xGex layer after anneal is much higher than after implant. This indicates that fluorine is transported into the Si1-xGex layer from the adjacent silicon, and is explained by the lower formation energy for vacancies in Ge than in Si. This accumulation of fluorine in the Si1-xGex layer during anneal is advantageous for devices like SiGe heterojunction bipolar transistors, where the boron must be kept within the Si1-xGex layer.

A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 µΩcm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000 °C. Collector/base reverse diode tics show a voltage dependence of approximately V1/2, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 x 1017 cm-3. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage.

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.