Sadegh Keshavarzi
About
My research project
Resilient and trustworthy data replication at wire speedThe project will exploit recent advances in networking, processor, and memory hardware, such as trusted execution environments (TEEs), byte-addressable non-volatile memory (NVRAM), and remote direct memory access (RDMA). It will develop novel data replication algorithms using software primitives offered by this hardware and formally verify their correctness.
To ensure a high degree of trustworthiness, the project outcomes will be extensively evaluated both analytically and empirically. The analytical evaluation will seek to develop new formal models to enable rigorous reasoning about correctness, computability, and costs of the proposed solutions, potentially establishing new lower and upper bounds. It will seek to develop frameworks to automate correctness proofs of its core components using tools such as the Isabelle/HOL theorem prover.
The empirical evaluation will explore integrating software prototypes into real-world applications, such as key-value stores, transactional data stores, and stream processing. The resulting prototypes will be evaluated using standard benchmarks, such as YCSB and TPC-C. The empirical evaluation will be conducted on the state-of-the-art RDMA/NVRAM/SGX testbed hosted by the Department of Computer Science, University of Surrey. The project will benefit from inputs and feedback of our industrial partners, such as NVIDIA, Arm, IBM and Stellar, for identifying case studies and validating its assumptions.
Supervisors
The project will exploit recent advances in networking, processor, and memory hardware, such as trusted execution environments (TEEs), byte-addressable non-volatile memory (NVRAM), and remote direct memory access (RDMA). It will develop novel data replication algorithms using software primitives offered by this hardware and formally verify their correctness.
To ensure a high degree of trustworthiness, the project outcomes will be extensively evaluated both analytically and empirically. The analytical evaluation will seek to develop new formal models to enable rigorous reasoning about correctness, computability, and costs of the proposed solutions, potentially establishing new lower and upper bounds. It will seek to develop frameworks to automate correctness proofs of its core components using tools such as the Isabelle/HOL theorem prover.
The empirical evaluation will explore integrating software prototypes into real-world applications, such as key-value stores, transactional data stores, and stream processing. The resulting prototypes will be evaluated using standard benchmarks, such as YCSB and TPC-C. The empirical evaluation will be conducted on the state-of-the-art RDMA/NVRAM/SGX testbed hosted by the Department of Computer Science, University of Surrey. The project will benefit from inputs and feedback of our industrial partners, such as NVIDIA, Arm, IBM and Stellar, for identifying case studies and validating its assumptions.
My qualifications
Publications
Recent advances in secure hardware technologies, such as Intel SGX or ARM TrustZone, offer an opportunity to substantially reduce the costs of Byzantine fault-tolerance by placing the program code and state within a secure enclave known as a Trusted Execution Environment (TEE). However, the protection offered by a TEE only applies during program execution. Once power is switched off, the non-volatile portion of the program state becomes vulnerable to rollback attacks wherein it is undetectably reverted to an older version. In this paper we consider the problem of implementing reliable read/write registers out of failure-prone replicas subject to state rollbacks. To this end, we introduce a new unified model that captures multiple failure types that can affect a TEE-based system and establish tight bounds on the fault-tolerance of register constructions in this model. We consider both the static case, where failure thresholds hold throughout the entire execution, and the dynamic case, where any number of replicas can roll back, provided these failures do not occur too often. Our dynamic register emulation algorithm, TEE-Rex , provides the first correct implementation of a distributed state recovery procedure that requires neither durable storage nor specialized hardware, such as trusted monotonic counters.
The advent of byte-addressable non-volatile memory (NVM) technologies has enabled the development of low-latency high-throughput durable applications, i.e., applications that are capable of recovering from full-system crashes. However, programming such applications is error-prone as efficiency gains often require fine-grained (programmer-controlled) management of low-level persistence instructions. We propose Mangosteen, a high-level programming framework that allows developers to transform an existing lineariz-able in-memory application to a corresponding durably lin-earizable version using NVM. Our framework's API consists of a set of callback hooks that interpose on an application's request processing flow with minimal developer effort. Man-gosteen executes client operations on DRAM and persists their effects using binary instrumentation and redo logging. Mangosteen's concurrency control facilitates batching of read-write requests to minimize the cost of persistence, while allowing read-only requests to execute concurrently. A novel intra-batch deduplication mechanism further reduces persistence overheads for common OLTP workloads. Our empirical evaluation results show that Mangosteen-enabled applications outperform state-of-the-art solutions across the entire spectrum of read-write ratios. In particular, the Mangosteen-based version of Redis demonstrates throughput gains of between 2×–5× in comparison to prior work.